When connecting logic circuits having different power source voltages, it is necessary to shift the logic level of an output signal from one logic circuit to the level of the logic circuit that receives the output signal. Typically, this operation is performed by a level shifting circuit.
FIG. 1 is a schematic diagram of a conventional level shifting circuit 10. The conventional level shifter 10 includes an inverter IV1, which operates from a power source voltage VDDL of an input side of the circuit. The circuit 10 also includes four transistors M1, M2, M3 and M4, which operate from a power source voltage VDDH of an output side of the circuit . . . The transistors M3 and M4 are p-channel MOS (PMOS) transistors, and the transistors M1 and M2 are n-channel MOS (NMOS) transistors. Transistors M1 and M2 are driven by an input signal VIN, the high level of which is VDDL, and the operation voltage of M1 and M2 is VDDH. When the level of the input signal is converted, a large delay is introduced into the converted signal, which has a detrimental effect on the output side circuit. For this reason, the conventional level shifter cannot be used as an interface between high-speed logic circuits that operate at different power source voltages.
FIG. 2 is a timing diagram illustrating waveforms for the input voltage VIN and the output voltage VOUT of the conventional level shifting circuit 10 of FIG. 1. FIG. 2 also illustrates a voltage waveform of node T2 of the circuit 10. As illustrated in the schematic diagram of FIG. 1, when the input voltage transitions from a low voltage L to a high voltage H, the output of inverter IV 1 applied to the gate of M1 transitions from H to L. The gate input of M2 also transitions from L to H. The output of transistor M1 at node T1 transitions from L to a second high voltage H′. The output of M2 at node T2 transitions from H′ to L, and the output of inverter IV2 applied as the output voltage VOUT transitions from L to H′.
With regard to the input transistor pair M1 and M2, the maximum voltage of the pair is VDDL, which is comparatively lower than VDDH. As a result, the initial saturation current is limited. Hence, latching speed is limited. The discharge path is through M2. Therefore, the operation of the circuit is delayed. FIG. 2 illustrates the time delay between the input voltage VIN and the output voltage VOUT. As a result of this delay, high-speed operation of the device is limited. The following equation defines the current of M2.
      I    M2    =                              μ          N                ⁢                  C          OX                    2        ⁢                  (                  W          L                )            M2        ⁢                  (                  VDDL          -                      V            THN                          )            2      where μN is carrier mobility, COX is gate capacitance, VTHN is threshold voltage, W is channel width and L is channel length.
With regard to the PMOS cross-coupled pair M3 and M4, since node T2 is charged by M3 and M4, the delay time is longer than that of a CMOS cross-coupled pair. Also, the load capacitances of nodes T1 and T2 are different. As a result, rising and falling times of the signals are different. Therefore, as shown in FIG. 2, the duty cycle of the waveforms are distorted.
One prior art level shifting circuit is disclosed in U.S. Pat. No. 6,043,699, the contents of which are incorporated herein in their entirety by reference. FIG. 3 contains a schematic diagram of the level shifting circuit of the '699 patent. Referring to FIG. 3, when a signal set to a voltage H(Va), analogous to VDDL, is input at terminal Tin, transistors NT51 and NT54 are in an on state. As a result of the on state of NT54, the potential at the gate of PT51 rises slightly. Also, since NT51 is in the on state, the potential at the gate of PT52 falls, and the potential at its drain rises. At this time, the potential at the gate of PT51 rises further, which lowers the potential at the output terminal Tout. Due to the function of NT54, which operates at the same time as NT51, high-speed operation is realized.